1. Field of the Invention
The present invention relates to a semiconductor integrated circuit testing device and method for testing functions of a semiconductor integrated circuit.
2. Related Background Art
Heretofore, in testing functions of a semiconductor integrated circuit including a logic circuit, a method has been adopted in which a pattern signal of a predetermined test pattern for testing the functions of the semiconductor integrated circuit is input to the semiconductor integrated circuit, and a signal value of an output pattern from the semiconductor integrated circuit is compared with an output pattern expected value, thereby judging whether the semiconductor integrated circuit is a defective or a non-defective (refer to “VLSI Test/Failure Analysis Technology,” Triceps Co., Ltd., pp. 119 and 120 (1992). The predetermined test pattern is a test pattern set such that an expected value of an output pattern which is to be output from the semiconductor integrated circuit when the pattern signal of the test pattern is input to the semiconductor integrated circuit becomes clear in advance through logic simulation and the like.
FIG. 23 is a block diagram, partly in circuit diagram, showing an example of a configuration of a conventional testing device for testing a semiconductor integrated circuit.
A signal terminal 102 of a test target IC 101 is connected to an input-output terminal 107 of a pin electronics 106.
The input-output terminal 107 is connected to a driver 109, a comparator 110, and a load 108. The driver 109 and the comparator 110 are connected to a pattern test device 111.
The pattern test device 111 reads out/writes a pattern signal used to test functions of the test target IC 101 from/to a memory 112, and when the signal terminal 102 is in an input state, sends the pattern signal read out from the memory 112 to the driver 109. Then, the driver 109 sends the pattern signal sent thereto to the test target IC 101. On the other hand, when the signal terminal 102 is in an output state, the comparator 110 receives a signal of an output pattern which has been output from the test target IC 101 through the signal terminal 102, and then the pattern test device 111 stores the output pattern in the memory 112.
A load current is caused to flow through the load 108 in correspondence to the output logic (a high level or a low level) at the signal terminal 102. Note that when the signal terminal 102 is in the output state, the driver 109 changes a state of an output over to a high impedance state to prevent an excessive current from flowing thereinto.
The pattern signal of the output pattern of the test target IC 101 stored in the memory 112 is compared with the expected value by a control device 113, and information related to whether or not the output pattern agrees with the expected value is displayed on a display device 114.
While only one signal terminal 102 of the test target IC 101 is illustrated in FIG. 23, in actuality, the plurality of signal terminals 102 exist. Then, the pin electronics 106 is provided in the same number as that of signal terminals in the test target IC 101. In addition, a power supply terminal 104 of the test target IC 101 is connected to a power supply 103 or the like built in the testing device, and a GND terminal 105 is connected to GND of the testing device.
The conventional testing device, for example, is configured as described above, and in general, an ISL (IC) tester or the like is used in such a testing device.
Now, in the conventional testing method based on the test pattern in which the expected value of the output pattern becomes clear, as the scale of a semiconductor integrated circuit to be measured becomes large, it becomes difficult to produce a test pattern in which all logic states are simulated, and hence an area which is undetected with the test pattern exists. As a result, there is a possibility that the nonconformity may occur such that in a machinery or the like having a semiconductor integrated circuit as one of constituent elements, when the machinery is used in the above-mentioned undetected area, the machinery does not normally operate.
When such nonconformity occurs, there is adopted a method in which logic simulation and failure simulation are carried out based on the fault phenomenon of the machinery, a test pattern is provided with which the fault phenomenon can be detected, and the test pattern is added to the original test pattern.
However, it is difficult to verify the logic state of the semiconductor integrated circuit when the semiconductor integrated circuit is used in the machinery in many cases. In addition, in the method based on the simulation, an enormous amount of data must be processed. Thus, a simpler method is required.
In addition, the conventional testing device shown in FIG. 23 has the following problems.
(1) Output states of a plurality of terminals such as output terminals and input-output terminals of the test target IC 101 must be monitored at all times by the comparator 110.
(2) The control device 112 must compare data of an output state, at the signal terminal 102 of the test target IC 101, detected by the comparator 110 with the expected value of the output pattern stored in the memory 112 at high speed.
(3) When the number of terminals of the test target IC 101 is large, and when a parallel test is carried out with which a plurality of test target ICs are tested at a time, the comparators 110 must be prepared in great numbers, and a capacity of the memory 112 must be increased. Thus, the scale of the LSI tester becomes necessarily large. In addition, the test/judgment must be simultaneously carried out for a plurality of terminals, which requires the advanced technique and thus inevitably leads to an increased cost of the testing device.